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EDS Mini Colloquim WIMNACT 39, Tokyo
Resistive Switching Memory
in Integration
Ming
Liu
Institute of Microelectronics, CAS
Feb.7, 2014
Outline
Motivation
RRAM Integration
Self-Rectifying RRAM
1D1R Integration
1k HfO2 based RRAM Test Chip
Summary
Flash Memory
Concepts proposed by D.
Kahng and S. M. Sze, Bell Lab,
1967
•Uses Fowler-Nordheim tunneling to erase
the memory
•Uses CHE or FN to program the memory
Kahng and S. M. Sze, Bell Systems
Technical Journal 46 (1967) 1288.
Total Semiconductor market : 300 B US$ in 2011; Memory occupied 23.9%
semiconductor market.
3
Flash Integration
Flash - E2PROM (NOR Type)
Control Gate
Floating Gate
Drain
NAND - E2PROM
Control Gate
Select Gate
SG (D)
Select Gate
WL1
WL2
WL3
WL14 WL15 WL16
Source
Drain
Bit Line
SG (S)
Basic unit
WL1
Source
Bit Line
SG (D)
Basic unit
WL1
WL2
WL3
WL4
WL2
WL3
WL14
WL15
WL16
SG (D)
WL16
1 Transistor / 1 Bit
18 Transistor / 32 Bit
NOR Type Flash: High Speed,Random Access per bit, Code Storage
NAND Type Flash : High Density,Block Access , Data Storage
Challenges of Flash scaling down
Crosstalk effect
Low No. of electron
Leakage current
Physical limitations exist!
–– leakage current
–– High voltage operations
–– Charge storage requirements of the dielectrics and reliability issues
–– Slow writing speed
3D Flash Architecture
Vertical structure
1st Mass Production of 3D VNAND
Integration Trend of Memory
 3D integration is the mainstream to enhance the storage density of memory.
 3D RRAM is one of the most promising candidates of Flash memory.
Outline
Motivation
RRAM Integration
Self-Rectifying RRAM
1D1R Integration
1k HfO2 based RRAM Test Chip
Summary
What is RRAM?
MIM: resistive switching
under electric field
Bipolar switching
Advantages of RRAM:







Simple device structure(MIM)
Good compatibility with CMOS process
Easy scaling down to 8 nm
Large on/off ratio (103~106)
Fast operating speed(~ns)
Good endurance (>106)
Good retention (>10years)
Unipolar switching
Opportunities for RRAM
Expected RRAM specs
Required memory specs
Working memory
Embedded NVM
Stand-alone NVM
Working memory
Embedded NVM
Stand-alone NVM
RRAM
RRAM is not suitable for working memory, but quite competitive
for embedded and stand-alone NVM application.
RRAM Integration: Active or Passive Array
Active
6~8F2
Ref. A. Chen, et al., IEDM 2005, pp. 765-768.
Passive
4F2
Ref. ITRS 2010.
Passive crossbar array structure is the best choice for high
storage density application!
3D RRAM Integration
 2D RRAM crossbar — 4F2
 3D RRAM crossbar — 4F2/n
Passive crossbar array structure is the good choice for high
storage density application!
Ref. ITRS 2010.
Sneaking Current in RRAM Integration
Vread
Open
Vread
Open
×
HRS
HRS
LRS
HRS
V=0
V=0
HRS
HRS
Open
When reading a HRS cell, if the
surrounded cells are all in HRS,
the reading is correct.
LRS
LRS
Open
If some surrounded cells is in LRS
and form a sneak current path, the
HRS cell will be misread as LRS.
How to Suppress Sneaking Current
(1). 1D1R
solution
(2). 1S1R
(3). SelfRectifying
Ref. I. G. Baek, et al., IEDM 2005; B. Cho, et al.,Adv. Mater. 2009
Current (A)
1E-3
200x
1E-5
bit ‘1’
20x
bit ‘0’
1E-7
1E-9
-3
-2
-1
0
Voltage (V)
1
2
How to Suppress Sneaking Current
Solutions
Schematic of the crosstalk effect
 1R: RRAM with self-rectifying effect
Asymmetric I-V curve
 1 Selector + 1 RRAM
Requirements of Selector:




High current density (Jselector>Jreset,RRAM)
High rectifying ratio or nonlinear factor
Compatible with CMOS
Low fabrication temperature (<400℃ set by the copper BEOL)
Outline
Motivation
RRAM Integration
Self-Rectifying RRAM
1D1R Integration
1k HfO2 based RRAM Test Chip
Summary
RRAM with (Au/ZrO2:Au/n+-Si)
Au
Au NC
10
-3
ZrO2
Device structure
Current (A)
n+-Si
2
10
-5
10
-7
3
Reset
Set
1
10
4
-9
-11
10
-4
-2
0
Voltage (V)
2
4
TEM image of the device
Typical I-V characteristics of the Au/ZrO2 :nc-Au/n+ Si device, it
showed low switch voltage and producible set and reset process.
Q Zuo, et al., J. Appl. Phys. , 106, 073724 (2009).
10
-4
10
-6
10
-8
10
Resistance ()
Current (A)
RRAM with (Au/ZrO2:Au/n+-Si)
LRS @0.5 V
HRS @0.5 V
-10
10
9
10
7
10
5
10
3
LRS @0.5 V
HRS @0.5 V
0
10
0
25
50
75
100
1
2
10
10
3
10
Time (s)
Cycle (#)
The Au/ZrO2:Au/n+-Si device demonstrated very good cycling and
retention characteristics.
Q Zuo, et al., J. Appl. Phys. , 106, 073724 (2009).
Self-rectifying Characteristics
-3
10
-4
10
-5
10
-5
Current (A)
Current (A)
10
700
-7
10
@ 0.5 V
@ -0.5 V
-6
10
-7
10
-8
10
-9
10
-9
10
0
-1.0
-0.5
0.0
Voltage (V)
0.5
1.0
50
Switching number
100
The Au/ZrO2:Au/n+ Si has a very good rectifying characteristics at
LRS. Ion/Ioff ratio is 700.
 After 100 cycling, its rectifying characteristics is still keeping very
well.
Q Zuo, et al., J. Appl. Phys. , 106, 073724 (2009).
Comparison in 2×2 Array
Resistance ()
10
Ron in sigle cell
Roff in sigle cell
Ron without rectifying
Roff without rectifying
Ron with rectifying
Roff with rectifying
4
10
3
10
2
10
1
B
A
C
Group A: HRS and LRS of Single device;
Group B: HRS and LRS of 2×2 array without rectifying;
Group C: HRS and LRS of 2×2 array with rectifying
0
2
4
6
8
Self-Rectifying RRAM for WORM Application
Cumulative Probability (%)
100
Area 200x200m
Read @ 1V
80
After PRG
Before PRG
60
40
x106
20
0
-10
10
11
2
-8
-6
-4
10
10
10
Current (A)
-2
10
10
Uniformity of the states before and after program
9
Resistance ()
10
• Large rectifying ratio (>104)
Read @ 1 V
7
10
• RHRS/RLRS >106
After PRG
Before PRG
5
10
• High uniformity
3
10
• Long retention time
1
10
0
10
1
10
2
3
4
10
10
10
Time (s)
Data retention
5
10
IEEE Electron Device Letters, 2010, 29, 43
US Patent 2012/0140543 Al
Self-Rectifying Mechanism
Ag
HfO2
Ag
n+-Si
Ag CF
 Based on the TEM results, we demonstrated that the CF composition in the oxideelectrolyte-based RRAM mainly consists of the electrode materials when using Cu, Ag
or Ni as electrode.
 By using semiconductor as another electrode, RRAM with self-rectifying effect can be
obtained, and the rectifying characteristics is controlled by metal and semiconductor
electrodes.
Adv. Mater. 24, 1844, 2012
The Role of Silicon for Self-Rectifying RRAM
n+-Si/a-Si/Ag
APL 2009
n+-Si/ZrOx/Pt
NiSi/HfOx/TiN
JAP 2009
VLSI 2011
 Metallic property of conductive filaments → Ohmic contact with metal electrode →
No rectifying characteristics.
 Highly doped Si is generally needed to guarantee a Schottky contact of CF with c-Si.
 Crystal Si is not expected for 3D integration.
A-Si to achieve Self-rectifying RRAM
TE
4200-SCS
DC bias/control
BE
Pt
WO3
a-Si
Cu
SiO2
Si(100)
Pt
WO3
a-Si
Cu
100 nm
Why a-Si?
Requirements of low fabrication temperature (<400℃ set by the copper BEOL)
for 3D integration.
√.CMOS compatible;√. Low temperature fabricate;√. Cheap;√. well controlled
process;
Memory Characteristics
Current (A)
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
RESET
SET
o
@ 25 C
1st cycle
after 10 3pulses
after 10 6pulses
-2
-1
0
1
2
Voltage (V)
3
The device exhibits bipolar switch behavior, there is 20 times window
between HRS and LRS;
Very excellent stability, even after 103 and 106 switch pulses, there is
still no obvious shift.
Uniformity of DTD and CTC
4
10
10
10
HRS
3
SET Voltage
2
6
10x window
5
4
LRS
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
Voltage (V)
Resistance ()
10
7
1
0
-1
RESET Voltage
-2
-3
-4
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
Excellent switching uniformity in cycle-to-cycle and device-to-device.
(data were collected from 100 switching cycles in random selected 10
cells)
IEEE Electron Device Letters, 2013, 34, 229
International Memory Workshop, 2013
Patent NO. 201210311109.8
Programming Speed and Cycling
8
8
10
Temp=25 ℃
7
10
Resistance ()
Resistance ()
10
HRS(bit’0’)
LRS(bit’1’)
6
10
1E-8
1E-7
1E-6
1E-5
P/E pulse width (sec)
Temp=25 ℃
HRS(bit’0’)
7
10
LRS(bit’1’)
6
10
0
10
2
10
4
10
6
10
8
10
10
10
12
10
P/E cycles (#)
Very fast switching speed, 30 ns both for write and erase;
Endurance is more than 109 switching cycles.
IEEE Electron Device Letters, 2013, 34, 229
International Memory Workshop, 2013
Patent NO. 201210311109.8
Self-Rectifying Characteristics
Obvious rectifying characteristics for both HRS and LRS after forming,
rectify ratio is 200;
Excellent reliability and reproducibility.
IEEE Electron Device Letters, 2013, 34, 229
International Memory Workshop, 2013
Patent NO. 201210311109.8
Origin of Self-Rectifying Behavior
0
10
0
10
RLRS~105Ω@0.5V
10
10
-6
10
Vf~3.2 V
If~10-4A
-8
-10
10
Pt
WO3
WO3
Cu
W
V
Rini~109Ω@0.5V
RLRS~105Ω@0.5V
-3
-2
-8
-10
10
-12
-1 0 1 2
Voltage (V)
3
4
Vf~6.5 V
If~10-4A
-6
10
10
-4
RLRS<102Ω@0.5V
-3
10
10
-12
10
10
-4
Current (A)
Current (A)
-4
10
10
-1
-2
Pt
WO3 V
a-Si
Cu
Rini~109Ω
@0.5V
Current (A)
-2
10
Vf~7 V
If>10-3A
-5
10
-7
10
Pt
a-Si V
Cu
Rini<106Ω@0.5V
-9
-2
0
2
4
Voltage (V)
6
8
10
-2 -1 0 1 2 3 4 5 6 7 8
Voltage (V)
Both of Cu/WO3/Pt and Cu/a-Si/Pt control sample show symmetrical I-V.
Rini of Cu/WO3 /Pt is three orders higher than that of Cu/a-Si/Pt, same with
Pt/WO3/a-Si/Cu device,
The WO3 layer is switched into LRS after forming, while the a-Si layer still
keeps in HRS.
The rectifying property of Cu/a-Si/WO3/Pt device is from the Schottky
contact of CF in WOx with a-Si.
Mechanism of Resistive Switching
The process of O2- ions trapping
andde-trapping on the vacancy site is
attributed to the switching behavior.
Filament composed of oxygen
vacancy is formed in SET process.
The recombination of O2- ions with
vacancy corresponds to the RESET
process.
Comparison of Various Technologies
The self-rectifying RRAM is a promising candidate for high density
application.
Outline
Motivation
RRAM Integration
Self-Rectifying RRAM
1D1R Integration
1k HfO2 based RRAM Test Chip
Summary
Comparison of Endurance and Reset
Current in unipolar and bipolar RRAM
Endurance cycles
10
10
Ref [7]: Ta2O5/TiO2
12
Ref [8]: HfOx
Ref [8]: HfOx/AlOy
10
10
8
10
6
Bipolar RRAM devices:
High endurance
Low reset current
Unipolar RRAM devices:
Low endurance
High reset current
Ref [5]: Ta2O5/TaOx
Ref [6]: TiOx/HfOx
4
10
0.0
Ref [5]: ZrOx/Ta2O5/AlO
0.1
0.2 0.4 0.6 0.8 1.0
Reset current (mA)
Most 1D-1R integration only suitable for Unipolar
RRAM .
[7] Y. Sakotsubo, et al., VLSI, p. 87, 2010.
[8] X.A. Tran, et al., VLSI, p. 44, 2011.
Bipolar 1D-1R Integration
Diode: Ni/TiOx/Ti
RRAM: Pt/HfO2/Cu
Y. T. Li, et al., Nanoscale, 5, 4785 (2013).
Diode and bipolar RRAM characteristics
(a) Typical I-V characteristics of Ti/TiOx/Ti and Ni/TiOx/Ti devices.
(b) Bipolar resistive switching characteristic of the Pt/HfO2/Cu RRAM cell.
Y. T. Li, et al., Nanoscale, 5, 4785 (2013).
Bipolar Resistive Switching of 1D1R Integration
The 1D-1R device exhibits bipolar switching characteristic, a selfcompliance behavior can be achieved during the set process;
 After 100 DC cycling, its bipolar switching characteristics is still
keeping very well.
Y. T. Li, et al., Nanoscale, 5, 4785 (2013).
Uniformity and Retention
Bipolar 1D-1R demonstrated very good uniformity
and retention characteristics.
Programming Speed
4
V1 OSC V2
3
Rs
Reset pulse
100ns/+3V
V1
V2
Voltage (V)
2
Read RRAM Diode Read
1
Read
0
-1
HRS
-2
-3
0
Transition from
HRS to LRS
Set pulse
100ns/-2.5V
1
2
3
4
Time (s)
Transition from
LRS to HRS again
5
6
Fast switching speed, 100 ns both for write and erase.
7
Multi-level storage and low power consumption
10
-1
10 AVR: average value
Current (A)
10
10
10
10
Vreset, Ireset@-2V
-3
Reset current (mA)
Vreset, Ireset@-2.5V
Vreset, Ireset@-1.5V
-5
-7
-9
Vset=-1.5V
Vset=-2V
Vset=-2.5V
-2
-1
0
1
2
3
STD: standard deviation
8
AVR=3.17mA
AVR=9.22mA
STD=1.39mA
STD=0.98mA
6
4
AVR=0.55mA
2 STD=0.21mA
0
Vset=-1.5V
Vset=-2V
Vset=-2.5V
Voltage (V)
Obvious Multi-level storage can be realized by controlling different voltage
during the SET process (Vset) ;
Ireset is found to reduce with the decrease of Vset.
Scalability of Ni/TiOx/Ti Selecting Diode
The forward current density is over 104 A/cm2 at 1V for 2×2 μm2 active area;
An even higher forward current density over 106 A/cm2 is expected from a
smaller area of 100×100 nm2 .
Y. T. Li, et al., Nanoscale, 5, 4785 (2013).
Comparison
References
RRAM
RRAM
Type
Diode
Diode Type
Compliance current
This work
Cu/HfO2 /Pt
Bipolar
W/TiOx/Ni
Schottky
Self-compliance
[1]
Pt/NiO/Pt
Unipolar
Pt/CuO/IZO/Pt
p-n junction
External current limiter
[2]
Pt/NiO/Pt
Unipolar
Pt/CuO/IZO/Pt
p-n junction
GIZO transistor
[3]
Pt/TiOx/Pt
Unipolar
Pt/TiOx/Pt
Schottky
External current limiter
[4]
Pt/ZnO/Pt
Unipolar
Pt/NiO/ZnO/Pt
p-n junction
External current limiter
[4]
Pt/ZnO/Pt
Unipolar
Pt/WO3/ZnO/Pt
Tunnel barrier External current limiter
1D1R structure generally can only use unipolar RRAM device, but the bipolar
RRAM has superior performance than unipolar RRAM. This work is a first
demonstration of a 1D1R structure using bipolar RRAM and Schottky diode.
Outline
Motivation
RRAM Integration
Self-Rectifying RRAM
1D1R Integration
1k HfO2 based RRAM Test Chip
Summary
1kb RRAM Test Chip Demo
RRAM cell
Integration solution
端口信号线
Cell_fail
内部控制
信号线
Write_fail
Write_trigger
ready
read
Write_finish
Latch
WD_ref
WD
WD_ref
WD
read
Latch_addr
readout
data
SA
SA_ref
SA
SA_ref
SA
read
P/E
DMA
DMA_port1
DMA
ARRAY
DMA_port2
addr
Reraseref2
Reraseref1
Rprogramref2
Rreadref2
Rprogramref1
DMA_wlv
Rreadref1
Address[9:0]
模拟信号
finish
readdata
writedata
operation
WD
P/E
read
Control unit
数据线
trigger
P/E
clk
rst
trigger
Latch
Periphery circuit design
1kb RRAM test chip
Device Structure and Bipolar Switching
Table. 1
BL
(c)
VSL
VWL
GND
+
+
+
GND
+
+
++
Operation VBL
RRAM
Forming GND
M5
V4
TE
M4
4 nm
V3
SET
WL
HfO2
RESET
Cu
SL
M3
5 nm
V2
400.0u
M2
Current (A)
V1
M1
CT
500 nm
Icc
200.0u
G
D
S
0.0
SET
-200.0u
-400.0u
-600.0u
RESET
-2
-1
0
1
Voltage (V)
2
3
1kb RRAM Test Chip Demo
Layout outlook
Data writing
Summary

RRAM with crossbar architecture attracts significant interests due to its
excellent scalability and 3D integration for high-density application.

The big challenge of this structure is how to eliminate crosstalk issue.

Self-rectifying RRAM and RRAM integration with 1D1R architecture
can suppress crosstalk leakage greatly.

RRAM with excellent memory performance and good reproducibility
are demonstrated with a self-rectifying characteristics, which can
suppress crosstalk leakage greatly.

Bipolar 1D-1R devices also exhibits good features in uniform switching,
satisfactory data retention, fast speed, as well as excellent scalability.

HfO2 based 1k test chip was demonstrated.
Thanks for your attention!
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