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Ultralow-Voltage Design and Technology
of Silicon-on-Thin-Buried-Oxide (SOTB)
CMOS for Highly Energy Efficient
Electronics in IoT Era
Nobuyuki Sugii
Low-power Electronics Association & Project
(LEAP)
http://tia-nano.jp/en/index.html
27 August, 2014
http://www.leap.or.jp/public_html/eindex.html
International Symposium on Leadging-edge SOI Technologies at KIT
1
Acknowledgments
This work is supported by New Energy and Industrial
Technology Development Organization and Ministry of
Economy, Trade, and Industry of Japan.
Universities and national institute in collaboration with LEAP:
The University of Tokyo
The University of Electro-Communications
Shibaura Institute of Technology
Kyoto University
Kyoto Institute of Technology
Keio University
Osaka University
Tokyo University of Science
The National Institute of AIST
Staffs of Renesas Electronics for chip fabrication
LEAP SOTB group members
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Key Messages and Questions
• IoT: Great number (exceed trillions in '20) of tiny
electronics and huge network traffic.
• Tiny electronics should be self-powered (zero-sum
energy). MEP operation, yet slow, recommended.
• SOTB offers highly energy efficient operation of CMOS
with considerably high (for IoT nodes) performance.
• How about chips in large systems?
• Scaling not significantly decrease energy due to
leakage and prefers higher fCLK.
• Further low Vdd at MEP possible?
• Retro scaling fCLK possible?
Solutions?
MEP: Minimum Energy Point
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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What is MEP operation?
Any transistor should work under the condition;
“lowest energy per operation”
Energy per operation:
Power:
P = CVdd2f + IleakVdd
E = CVdd2 + IleakVdd/af
AC power leakage
a: activity
MEP
B. Zhai et al. VLSI Symp. (2006)
“MEP operation”, at near Vdd=0.4V, maximizes efficiency, but very slow
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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MEP operation is very slow
MEP here
Important parameters
to optimize energy
27 August, 2014
A. Wang et al. IEEE JSSC 40, p. 310 (2005)
International Symposium on Leadging-edge SOI Technologies at KIT
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Miniaturization increases Vdd@MEP
High-performance flavor also prefers higher Vdd
(E determined by Eactive can disregard leakage power!).
LEAKAGE should DECREASE with SCALING for MEP op.
A. Chandrakasan et al. Proc. IEEE 98,
191 (2010)
27 August, 2014
D. Bol, Thesis, Université catholique
de Louvain (2008)
International Symposium on Leadging-edge SOI Technologies at KIT
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Higher fCLK and variability increase E
Higher fCLK degrades
efficiency
Variability tolerant design
increases power (area) and
decreases speed (logic depth)
This trend still
unchanged
Kao et al. JSSC 37, p. 1545 (2002)
27 August, 2014
D. Blaauw et al. ISCAS 2006, p. 32 (2006)
International Symposium on Leadging-edge SOI Technologies at KIT
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Adaptive control is efficient
EDP, not MEP!
No Knob
Bulk FBB
Single Knob
FDSOI ZBB
Dual Knobs
Miyazaki et al., ISSCC, p.40 (2002)
FDSOI FBB
P. Flatresse et al., ISSCC, 24.3 (2013)
“Leakage (Vth) control=Adaptive body biasing” (ABB),
depending on a (activity), is a key technology in terms of
power-speed tradeoff.
ABB minimizes Energy!
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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fCLK increase already stopped
Tr. # increases
fCLK
Why not decreases?
Power
Perf./CLK
Why not increases?
"The Free Lunch Is Over," http://www.gotw.ca/publications/concurrency-ddj.htm
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Interest as a device engineer
• Operation should be done at MEP.
• More performance (not fCLK) at MEP.
• Smaller variability & leakage can
decrease Vdd at MEP.
• Adaptive control capability significant.
• High reliability at low Vdd (soft error).
Already proven for thin-BOX FDSOI.
• New steep transistors in a long term.
TFETs are improving their performance year by year.
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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SOTB (Silicon on Thin BOX)
Ultralow-voltage core circuit
PMOS
Hybrid-bulk I/O circuit
NMOS
V (core)
Vbp dd
GND
n GP
deep n well
p substrate
PMOS
NMOS
Vcc (I/O)
Vbn
p GP
n well
GND
p well
p substrate
ultrathin BOX (10 nm)
ultrathin SOI (12 nm)
Ultrathin SOI / BOX:
Low-impurity channel:
Ultrathin BOX:
Vth adjustment Imp.:
Same layout as bulk:
-
Excellent SCE immunity
Suppression of Vth variation
Less Vth sensitivity to tSOI
Back-gate bias control
Vth control (Multiple Vth)
Easy design porting
R. Tsuchiya et al., IEDM2004. / N. Sugii et al. T-ED 57 p. 835. / Y. Yamamoto et al. VLSI2012-3.
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Device/process technology
• Stay on 65 nm (low leakage, we can go
smaller if leakage can reduce).
"65 nm is the best node for IoT," R. Aitken (ARM), VLSI 2014
• Gate stack: stay on poly-gate, and use
high-k to tune EWF (LP~LSTP option)
• Impurity-profile tuning below BOX
(multiple Vth control)
• High-quality epitaxial growth (small R &
small on-current variation )
• Hybrid bulk for I/O and ESD
H. Makiyama et al., IEEE IMFEDK, p. 42 (2011).
Y. Yamamoto et al., VLSI 2012 & 2013
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International Symposium on Leadging-edge SOI Technologies at KIT
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SOTB integration (SRAM & logic)
Hf or Al incorporation
for “Quarter-gap” work function
Cross sectional TEM of
SRAM region
Poly-Si
SiON
Epi
SOI~12nm
BOX=10nm
GP~1018/cm3
PG
Si-sub
PU
PD
The smallest transistors in ULSI
(of each technology) are in SRAM.
27 August, 2014
2Mbit 6T-SRAM
bit cell area :0.54 μm2
same layout as bulk
International Symposium on Leadging-edge SOI Technologies at KIT
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Benchmark of Vth variation
FDSOI (SOTB) has better AVT values among
various transistor structures
AVT is
proportional to
gate-oxide
thickness Tinv.
Data from conference papers (2010-2012)
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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1M-Variability of Vth and Ion
Cumulative probability
6
SOTB
4
Bulk
×2 worst
performance
2
0
-2
Same
worst
leakage
-4
-6
Bulk
0
0.2 0.4 0.6 0.8
Vth(V)
SOTB
1M Trs
L=0.06um
W=0.14um
0
40
80
120
Ion(uA) @ VDD=1.2V
·The distribution has no tail (normal distr.).
·SOTB have ×2 worst on current than bulk of same
worst leakage transistor
Y. Yamamoto et al. VLSI Tech. 2013.
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International Symposium on Leadging-edge SOI Technologies at KIT
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0.37-V SRAM (2 Mbit) operation
0
Measured
data
Fail Bit_σ
-1
-2
-3
-4
-5
Vmin
=0.37V
0
0.2 0.4 0.6 0.8
VDD(V)
Significant Vmin improvement
thanks to small variability of SOTB
27 August, 2014
-0.4V
1
Y. Yamamoto et al.
VLSI Tech. 2013.
International Symposium on Leadging-edge SOI Technologies at KIT
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Speed and leakage control by back bias
5.5nsec
1
Active
0.1
0.2 0.4 0.6 0.8
VDD(V)
1
1000
Cell leakage current (pA)
Access time (nsec)
10
2-Mbit SRAM
1.2
Operates >>>10 MHz
at VDD=0.4 V
1/200
by RBB of 1.3V
100
10
1
Active
Standby
1.2-pA cell leakage
current for standby mode
Y. Yamamoto et al. VLSI Tech. 2013.
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Robustness against temperature
SRAM stability simulation
Read
limit
■High temperature
→Vth↓
→Read Margin degrade
■Vth↑ by RBB
→Vmin recover <0.4V
Write
limit
Vmin(V)
0.5
0.4
0.3
0.2
Y. Yamamoto et al. VLSI Tech. 2013.
27 August, 2014
Measured
data
RT
80°C
0
0.2
|Vb| (V)
International Symposium on Leadging-edge SOI Technologies at KIT
0.4
18
SOTB is fast and efficient at low Vdd
By 40% smaller delay at 0.4 V (same VT)
VT=(Vthn-Vthp)/2
Same Cload, improved Ieff/Ioff characteristics (S and DIBL)
Makiyama et al., Jpn. J. Appl. Phys. 53, 04EC07 (2014)
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Small local delay variability
Small N dependence: mainly global variability
(N: number of ring osc. stages)
Makiyama et al., Jpn. J. Appl. Phys. 53, 04EC07 (2014)
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Soft error immunity
6T-SRAM
FF
Single event upset (neutron):
> one-order improvement
Multiple-cell upset (neutron):
> two-order improvement
Alpha:
> two-order improvement
Neutron:
> one-order improvement
Courtesy: Prof. Hashimoto (Osaka Univ.)
NSREC 2014 (to be published in TNS)
27 August, 2014
Courtesy: Prof. Kobayashi (Kyorto Inst. Tech.)
RADECS 2013 (to be published in TNS)
International Symposium on Leadging-edge SOI Technologies at KIT
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Design environment
SOTB circuits can be designed through the conventional flow.
Only slight modifications are necessary.
Design Compiler
RTL
Logic synthesis
Formality
Logic verification
BSIM4
HiSIM-SOTB
std. cell
layout
SPICE
Libraries
Parasitic RC
timing constraints
IC Compiler
(SoC Encounter)
Place and route
PrimeTime
Timing analysis
STAR RC
P&R tech. lib.
Virtuoso/Composer
Calibre
Physical verification
Mask layout
27 August, 2014
Verification rules
DRC, LVS, ANT, dummy
Silicon verification OK!
International Symposium on Leadging-edge SOI Technologies at KIT
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Very low energy in 32-bit MCU
1.47 mm
SRAM
SRAM
50k gate logic
SRAM
SOTB ULV circuit
6T-SRAM
144 kByte
32-bit
RISC CPU
Bulk
I/O
circuit
UART
interface
SRAM
1.43 mm
SPI
interface
ROM
interface
GP
interface
CPU:
In-order five-stage pipeline
Harvard architecture (instruction and data on separate buses)
Instruction and data cache (not implemented in this chip)
Ishibashi et al., COOL Chips XVII (2014)
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Power line structure
Ishibashi et al.,
COOL Chips
XVII (2014)
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Very low energy in 32-bit MCU
-0.3V
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Sleep current control
VBB generator design with very small current (<< uA) has
been done thanks to negligibly small substrate leakage.
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Perpetuum Mobile Computing
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Key Messages and Questions
• IoT: Great number (exceed trillions in '20) of tiny
electronics and huge network traffic.
• Tiny electronics should be self-powered (zero-sum
energy). MEP operation, yet slow, recommended.
• SOTB offers highly energy efficient operation of CMOS
with considerably high (for IoT nodes) performance.
• How about chips in large systems?
• Scaling not significantly decrease energy due to
leakage and prefers higher fCLK.
• Further low Vdd at MEP possible?
• Retro scaling fCLK possible?
Solutions?
MEP: Minimum Energy Point
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Energy benchmarking
Vdd@MEP around 0.3-0.5 V regardless of tech.
Frequency not high @MEP, though,
FDSOI (SOTB/UTBB) has significant speed gain
Reference
ISSCC
2010
ISSCC
2012
ISSCC
2012
ISSCC
2014
COOL
To be
Chips'14 (2014)
Technology
180-nm
Bulk
32-nm
Bulk
22-nm
Tri Gate
28-nm
UTBB
65-nm
SOTB
65-nm
SOTB
IP
32-bit
M3
IA-32
32-way
SIMD*
DSP
32-bit
RISC
DSP
Vdd range
0.350.75 V
0.281.2 V
0.281.1 V
0.391.3 V
0.221.2 V
0.21.2 V
Vdd @ MEP
0.4 V
0.45 V
0.28 V
0.53 V
0.35 V
0.55 V
f @ MEP
73 kHz
60 MHz
17 MHz
460 MHz 14 MHz
Emin
28.9 pJ
170 pJ
6.5 pJ*
62 pJ
13.4 pJ
*highly parallel processing
(154 GOPs/W)
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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fCLK retro scaling possible?
Type
Micro proc.
Mobile proc. "Dedicated"
(DSP)
(BB, MPEG)
# op. per cycle
27
500
5,000
fCLK
3 GHz
80 MHz
25 MHz
Perf. (GOPS)
81
40
125
P (W)
95
0.2
2.3m
Efficiency (OP/nJ)
0.85
200
54,348
Energy (pJ)
1173
5.0
0.0184
Vdd (V)
~1.0?
~0.9?
0.55
"Dedicated" means ultra-parallelism dedicated design.
How can we increase the portion of such highly-efficient
"dedicated" engines in a chip?
Data cited from B. Brodersen (S3S 2013) & ISSCC 2013 papers
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Efficiency of Top 500 Supercomputers
Decreasing E as low as possible down to MEP
is mandatory even in HP applications.
1000
as of Nov. 2013
400 MW for Exa flops!
Power (MW)
100
Mega solar
power
plant
10
Can improve E
by two orders?
1
0.1
http://www.top500.org/
0.01
0.1
1
10
100
1000
Performance (Pflops)
Already many GPUs are used.
27 August, 2014
What comes next?
International Symposium on Leadging-edge SOI Technologies at KIT
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Higher-efficiency approach
Tiny electronics
• Higher performance with
slower fCLK (MEP)
• Zero-sum power with
harvesting
• Non-volatile logic
eliminating leakage
• Intermittent operation
• Reduce communication
data rate (compression)
• Low-voltage I/O
• Dedicated multiple
components?
• ....
• ....
• .... still many issues
27 August, 2014
Large systems
• Higher performance with
slower fCLK (MEP)
• Energy efficient and
wide-band memory?
• Wide-band yet slower fCLK
communication (I/F?)
• Reduce sequential
fraction (Amdahl's law)
• Reconfigurable
interconnect
• Dedicated multiple
components?
• ....
• ....
• .... still many issues
International Symposium on Leadging-edge SOI Technologies at KIT
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Examples: efficient components
Flex Power FPGA
Cool Mega Array
Reconfigurable wiring
with Atom SW (LEAP)
Atom SW
Processing
Elements
ON
LVT
Critical Path
HVT
HVT & LVT by VBB
~1/100 Leakage
Nat. Inst. AIST
27 August, 2014
Ru
Micro
controller
Efficiency (MOPS/mW)
Fine-grain VBB control
of each LUT and MUX
100
80
60
40
Alpha Blender
Vdd=0.3V
Vdd=0.4V
SOTB
VBB=
VBB=
-0.2V 0V
0V
VBB=
0.4V
0.2V
0.4V
-0.4V 0V
20
0
Vdd=0.8V
0
OFF
Bulk
50
Frequency (MHz)
100
Reconfigurable logic
minimizing E by VBB
Keio University
Cu
Solid Electrolyte
Data
CLK
compress. cycle
E (nJ)
CPU:
MSP430
177
2.89
Offloader:
Atom SW
8.3
0.135
ratio
0.047
0.044
Reconfigurable offloader
reduces CLK cycle and E
LEAP
International Symposium on Leadging-edge SOI Technologies at KIT
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Summary
• Serious issue in IoT Era: Energy saving.
• CMOS circuits should operate at MEP at
•
•
•
•
any time.
Hetero integration of "Dedicated"
(parallel) engines is expected.
Super steep transistor is promising,
in the long term.
In the short term, thin-BOX FDSOI
(SOTB) is our recommendation.
Roughly one order improvement in
energy. Why not use FDSOI?
27 August, 2014
International Symposium on Leadging-edge SOI Technologies at KIT
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Thank you for your attention!
27 August, 2014
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Appendix
Publications relating SOTB (from Hitachi/Renesas, Tokyo University, and LEAP)
R. Tsuchiya et al., IEDM 2004, p. 631.
T. Ohtou et al., Electron Device Letters, 28, p. 740 (2007).
T. Ishigaki et al., SSDM 2007, p. 886.
T. Ishigaki et al., Jpn. J. Appl. Phys., 47 (4), p. 2585 (2008).
R. Tsuchiya et al., IEDM 2007, p. 475.
Y. Morita et al., VLSI Technology 2008, p. 166.
T. Ishigaki et al., ESSDERC 2008, p. 198.
T. Ishigaki et al., Solid-State Electronics, 53, p. 717 (2009).
N. Sugii et al., SSDM 2008., p. 880.
N. Sugii et al., Jpn. J. Appl. Phys., 48 (4), 04C043 (2009).
N. Sugii et al., IEDM 2008, p. 249.
R. Tsuchiya et al., VLSI 2009, p. 150.
N. Sugii et al., Trans. Electron Devices, 54, p. 835 (2010).
T. Ishigaki et al., IRPS 2010, p. 1049.
T. Hiramoto et al., SOI Conference 2010, p. 170 (2010).
T. Ishigaki et al., Trans. Electron Devices, 58, p. 1197 (2011).
J. Nishimura et al., IEEE ULIS 2011, (2011).
A. Shima et al., Jpn. J. Appl. Phys., 50 (4), 04DC06 (2011).
H. Makiyama et al., IEEE IMFEDK, p. 42 (2011).
H. Makiyama et al., EUROSOI 2012
Y. Yamamoto et al., VLSI 2012
T. Mizutani et al., SNW 2012
T. Mizutani et al., Jpn. J. Appl. Phys., 52, 04CC02 (2013).
Y. Yamamoto et al., VLSI 2013, T212
H. Makiyama et al., IEDM 2013, 33.2
H. Makiyama et al., Jpn. J. Appl. Phys., 53, 04EC07 (2014) open access
N. Sugii et al., JLPEA. 2014, 4, 65-76; doi:10.3390/jlpea4020065 (open)
K. Ishibashi et al., COOL Chips XVII, Yokohama 2014.
27 August, 2014
SOTB
Variability simulation
SOTB/bulk hybrid
SOTB/bulk hybrid
SRAM, back-bias effect
Variability, multi-Vth
RO, back-bias effect
RO, back-bias effect
Variability
Variability
Variability
SRAM, analog, reliability
Variability
HC & NBTI reliability
Variability
HC & NBTI reliability
RTN
Metal S/D process
Vth design
Vth design
Low-Vdd operation
Variability (on-current)
Variability (S factor)
Low-Vdd SRAM
RO delay VBB control
RO delay variability
Review
CPU results
International Symposium on Leadging-edge SOI Technologies at KIT
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