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Week3 : Circuits & Layout
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
2
Complementary CMOS 1.4.3
Complementary CMOS logic gates
– nMOS pull-down network
– pMOS pull-up network
inputs
– a.k.a. static CMOS
(as known as)
pMOS
pull-up
network
out
nMOS
pull-down
network
Pull-up OFF
Pull-up ON
Pull-down OFF
Z (float)
1
Pull-down ON
0
X (crowbar)
Complementary CMOS gates always produce 0 or 1
Rule of Conduction Complements
inputs
– Pull-up network is complement of pull-down
– P Parallel
N series, P series
N parallel
N series
Series and Parallel (3)
a
a
a
a
a
g1
0
0
1
1
g2
0
1
0
1
b
b
b
b
b
OFF
OFF
OFF
ON
P Parallel
complement
P series
N parallel
complement
3
pMOS
pull-up
network
out
nMOS
pull-down
network
4
Conduction Complement
Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS
Activity:
– Sketch a 4-input CMOS NOR gate
Pull-up
pulldown
A
B
C
D
Y
5
Compound Gates (1) 1.4.5
Compound gates can do any inverting function
Ex: Y = A × B + C × D
Pull-down network
A× B C × D
C
A
D Pull-up
B
network
Pull-up network
A× B
Y
A
C
B
D Pull-down
network
A× B + C × D
C×D
A× B + C × D
6
Compound Gates (2)
To achieve the same driving ability
The same output R
Wn =6
Wn =6
Wp =3
Wn =2
Wn =2
Wn =1
A
Wp =12
B
Wp =12
C
Wp =12
D
Wp =12
Wp =6
Wp=6
Wp=3
Wn =2
Y
Wn =1
Wn =1
Wn =1
Wn =1
Wn =2
Wn =2
7
Example: O3AI
Find the schematic and decide all Wn and wp
Y = ( A + B + C) × D
Y = ( A + B × C) × D + E
A
B
C
D
Y
D
A
B
C
8
Pass Transistors 1.4.6
Strength of signal
– How close it approximates ideal voltage source
1
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
– But degraded or weak 1
pMOS pass strong 1
– But degraded or weak 0
Thus nMOS are best for pull-down network
VT
0
0
VDD
0
1
VDD−VT
9
Transmission Gates 1.4.6
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
10
Tristates 1.4.7
Tristate buffer produces Z when not enabled
EN
A
Y
0
0
Z
0
1
Z
1
0
0
1
1
1
Transmission gate acts as tristate buffer
–Only two transistors, but nonrestoring tristate
–Noise on A is passed on to Y
11
Tristate Inverter
Tristate inverter produces restored output
–Violates conduction complement rule
–Because we want a Z output
in
en
out
12
Multiplexers (MUX) 1.4.8
2:1 multiplexer chooses between two inputs
Y = S ⋅ D1 + S ⋅ D0
S
D1
D0
Y
0
X
0
0
0
X
1
1
1
0
X
0
1
1
X
1
MUX Gate-Level implementation
D1
S
D0
Y
D1
S
D0
4
4
2
4
14 transistors
Y
13
Inverting MUX
Inverting multiplexer
–pair of tristate inverters
–Or use complementary logic
–Essentially the same thing
Y = S ⋅ D1 + S ⋅ D0
Noninverting multiplexer adds an inverter
S
D0
D0
D1
S
Y
Y
D1
Pair of tri-state inverters
Complementary logic
14
Transmission Gate MUX
Nonrestoring mux uses two transmission gates
How many transistors are needed ? 6
S0
S1
D0
S0
S1
D1
D0
0
Y
D1
1
D2
0
D3
1
0
D2
1
D3
15
D Latch 1.4.9.1
When CLK = 1, latch is transparent (sense)
–D flows through to Q like a buffer
When CLK = 0, the latch is opaque (latch)
–Q holds its old value independent of D
D
Latch
CLK
latch
Q
sense
latch
16
D Latch Design
Multiplexer chooses D or old Q
CLK
D
1
Q
Q
0
17
D Flip-flop 1.4.9.2
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, master-slave flip-flop
Flop
CLK
D
CLK
Q
D
Q
Master latch
Slave latch
CLK
CLK
latch
QM
D
CLK
CLK
Q
CLK
CLK
sense
CLK
sense
CLK
latch
當CLK由0 1的正緣區間內,資料被DFF的master取樣住 :
1.前半週期(CLK=1),資料値鎖在master latch,slave latch此時跟著master latch的値,即資料値
2.後半週期(CLK=0),資料値鎖在slave latch,此時slave latch會無視master latch的值
3.無論前半週期或後半週期,slave latch輸出都等於資料値,所以輸入資料被取樣後會存在DFF一個clock cycle
18
Race Condition
Back-to-back flops can malfunction from clock skew
– hold-time failure or race condition
Q1
Flop
Flop
CLK1
DFF1
ok
DFF2
C
Q2
A
B
B
C
C
CLK1
A
B
C
CLK2
Q2
B
CLK2
CLK1
wrong Q1
A
Q1
A
CLK2
A
B
C
ok
Q2
A
B
1. DFF2跟DFF1同時取樣 或 DFF2提早DFF1取樣,DFF2會取樣到DFF1在前一週期的取樣値
2. DFF2落後DFF1取樣,則DFF2可能會取樣到DFF1在目前週期的取樣値
C
19
Nonoverlapping Clocks
Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
We will use them in this class for safe design
– Industry manages skew more carefully instead
2
1
Master
Slave
QM
Wrong operation
D
2
1
2
1
2
1
Sense
Latch
Sense
Latch
Latch
Sense
Latch
Sense
Latch
Sense
Sense
Latch
Latch
Sense
20
Gate Layout 1.5.4
Layout : time consuming
– Design gates to fit together nicely
– Build a library of standard cells
Standard cell design methodology
– VDD and GND should abut 鄰接(standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts
21
Example: INV & NAND3
Horizontal n-diffusion and p-diffusion strips
細長片
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
VDD rail
P-diffusion
polysilicon gates
N-diffusion
GND rail
22
Wiring Tracks
A wiring track is the space required for a wire
– 4λ width, 4λ spacing from neighbor = 8λ
λ pitch
– TSMC 90nm process
λ=45um
Transistors also consume one wiring track
4λ
8λ
4λ
4λ
contact
via
(4+2+2)λ
4λ
23
Well spacing
Wells must surround transistors by 6 λ
– Implies 12 λ between opposite transistor flavors
– Leaves room for one wire track
6λ
6λ
24
Area Estimation
4λ
4λ
8λ
8λ
8λ
8λ
4λ
6λ
6λ
8λ
8λ
8λ
4λ
25
Stick Diagrams 1.5.5
Stick diagrams help plan layout quickly
–Need not be to scale
乾 擦掉,抹去
–Draw with color pencils or dry-erase markers
VDD
VDD
A
A
B
C
metal1
poly
c
ndiff
pdiff
Y
GND
INV
Y
GND
NAND3
contact
26
Example (1)
Sketch a stick diagram for O3AI and estimate area
– Y = ( A + B + C) × D
A
B
C
D
Y
D
A
B
C
27
Draw a stick diagram
CKb
CK
CK
ob
CK
in
CKb
o
CKb
CKb
CK
inb
28
Homework 3
1.設計一正緣取樣DFF (PMOS/NMOS尺寸自
訂) ,架構圖如右所示
輸入參考時脈與測試資料 , 說明你的DFF是
操作正確的
2
1
Master
Slave
QM
D
2
1
2
2.接著完成如右下所示的4bit位移暫存器, 觀察
d1訊號30個參考時脈周期
1
2
3. 增加參考頻率值 , 值到位移暫存器輸出波
形發生錯誤來得到最大操作頻率值
降低供應電壓, 值到d1輸出波形發生錯誤來得
到最低操作電壓值
觀測電路內部結點波形找出電路會發生錯誤
的原因
d
1
d
X0 q
D
X1 q
d
D
X2 q
d
D
X3 q
D
500MHz
(Rise/fall time:0.1ns)
d1
d2
d3
d4
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